Tektronix Encore

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Tektronix BSA125C
BERTScope 12.5 Gb/s Pattern Generator and Error Analyzer

Telecommunication and Wireless >> Bit Error Ratio Testers (BERT) >> BERTScope 12.5 Gb/s Pattern Generator and Error Analyzer
Rent Used Test Equipment
Manufacturer: Tektronix
Model: BSA125C

Tektronix BSA125C BERTScope 12.5 Gb/s Pattern Generator and Error Analyzer

Electronic Test and Measurement Equipment

Tektronix BSA125C BERTScope 12.5 Gb/s Pattern Generator and Error Analyzer Product Datasheet Download Product Datasheet

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Product Overview

TEKTRONIX BSA125C

TheTektronix BSA125C  BERTScope™ Tester provides a new approach to signal integrity measurements of serial data systems. Perform bit error ratio detection more quickly, accurately, and thoroughly by bridging eye diagram analysis with BER pattern generation. The BERTScope BSA Series enables you to easily isolate problematic bit and pattern sequences, then analyze further with seven types of advanced error analysis that deliver unprecedented statistical measurement depth.

  • Pattern Generation and Error Analysis, High-speed BER Measurements up to 12.5 Gb/s
  • Integrated, Calibrated Stress Generation to Address the Stressed Receiver Sensitivity and Clock Recovery Jitter Tolerance Test
  • Requirements for a Wide Range of Standards
  • Sinusoidal Jitter to 100 MHz
  • Random Jitter
  • Bounded, Uncorrelated Jitter
  • Sinusoidal Interference
  • Spread Spectrum Clocking

The Tektronix BSA125C BERTScope offers electical stressed eye testing for:

  • PCI Express
  • 10/40/100 Gb Ethernet
  • SFP+/SFI
  • XFP/XFI, OIF/CEI
  • Fibre Channel
  • SATA
  • USB 3.0
  • Jitter Tolerance Compliance Template Testing with Margin Testing
  • Physical Layer Test Suite with Mask Testing, Jitter Peak, BER Contour, and Q-factor Analysis for Comprehensive Testing with Standard or User-defined Libraries of Jitter Tolerance Templates
  • Integrated Eye Diagram Analysis with BER Correlation
  • Optional Jitter Map Comprehensive Jitter Decomposition – with Long Pattern (i.e. PRBS-31) Jitter Triangulation to Extend BER-based Jitter Decomposition Beyond the Limitations of Dual Dirac TJ, DJ, and RJ for a Comprehensive Breakdown of Jitter Subcomponents
  • Patented Error Location Analysis™ enables Rapid Understanding of your BER Performance Limitations and Assess Deterministic versus Random Errors, Perform Detailed Pattern-dependent Error Analysis, Perform Error Burst Analysis, or Error-free Interval Analysis
  • PCIe 2.0 Receiver Testing
  • F/2 Jitter Generation for 8xFC and 10GBASE-KR Testing

See alternative SyntheSys Research BSA12500B

 

Click to see all the models in this series

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Axiom has been a huge help to our success in the high demand of Silicon Valley. We are pleased to continue to work with Axiom for our equipment needs.


-- Tony W.
Newark, CA




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